DOCUMENT NUMBER: REV:
M0420SD-204SDAR1-3
00
DATE PRINTED:
SHEET:
STANDARD NAME:
Vcc
0.2V
4.5V
t
OFF
RS, STB
t
IRSTD
t
RVCC
Figure 1.
Power-up Internal Reset Timing
RST/
t
RSTL
RS, STB
t
ERSTD
t
f
t
r
Figure 2.
External Reset Timing
4.7.2 MOTOROLA M68-TYPE PARALLEL INTERFACE TIMING
(See Figures 3 and 4)
Item
Symbol Min. Max. Unit
RS, R/W setup time
tAS
20
-
ns
RS, R/W hold time
tAH
10
-
ns
Input signal rise time
tr
-15ns
Input signal fall time
tf
-15ns
E pulse width high
PWEH
230
-
ns
E pulse width low
PWEL
230
-
ns
Write data setup time
tDS
80
-
ns
Write data hold time
tDH
10
-
ns
E cycle time
tCYCE
500
-
ns
Read data delay time
tDD
-
160 ns
Read data hold time
tDHR
5-ns
Note: All timing is specified using 20% and 80% of VCC
as the reference points.
7 of 24
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